1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a trench capacitor cell. Specifically, the invention involves the controlled formation of bottle trench capacitors.
2. Description of Related Art
As the integration density of a Dynamic Random Access Memory (DRAM) steadily increases, it becomes necessary to reduce the memory cell size. The memory cell size is primarily determined by the minimum resolution dimension of a lithographic technique, the overlay tolerances between the different features and the layout of these features. At the same time, it is necessary to maintain the minimum required storage capacitance to reliably operate the DRAM. To meet both the cell size requirement and the storage capacitance requirement, a trench capacitor was invented; the simple single device/capacitor memory cell has been altered to provide the capacitor in a vertical dimension. In such designs, the capacitor is formed in a trench in the surface of the semiconductor substrate.
The article "Trench and Compact Structures for DRAMs" by P. Chatterjee et al., International Electron Devices Meeting 1986, Technical Digest paper 61, pp. 128-131, describes variations in trench cell designs through 16 Mb DRAM designs, including the Substrate Plate Trench (SPT) cell described in more detail in U.S. Pat. No. 4,688,063 issued Aug. 18, 1987, to Lu et al. and assigned to the assignee of the instant invention. Additionally, U.S. Pat. No. 5,348,905 issued to Kenney on Sep. 20, 1994, entitled, "METHOD OF MAKING DIFFUSED BURIED PLATE TRENCH DRAM CELL ARRAY", teaches the basic elements and process steps for fabricating a buried plate DRAM cell structure.
In the memory cell, a deep trench is formed in a silicon substrate in a direction perpendicular to the main surface thereof and a memory capacitor is typically formed on the side wall of the trench. The concept of making a semiconductor memory device having a capacitor on the side surface of the trench is commonly known in the prior art.
However, as the size of a DRAM is scaled down by a factor of f (feature size), the trench storage node capacitance decreases by a factor of f. Therefore, it is important to develop methods to increase the storage capacitance.
One method employed to increase capacitance is to widen the bottom portion of the trench, thus, increasing the surface area and creating a "bottle shaped" capacitor. However, in order to space the capacitors close together, control of the etching process used to widen the bottom portion becomes a governing factor. Chemical dry etching is predominantly used in the prior art for creating the bottle-shaped portion of the capacitor.
In U.S. Pat. No. 5,112,771 issued to Ishii, et al. on May 12, 1992, entitled, "METHOD OF FABRICATING A SEMICONDUCTOR DEVICE HAVING A TRENCH", the bottom region of a trench capacitor is enlarged. This is accomplished by leaving a silicon oxide film on the upper side wall of a trench, and enlarging the width of the exposed bottom portion of the trench by an isotropic dry etching process. Since the silicon substrate is isotropically dry etched, it is etched not only in the vertical direction to the surface of the substrate, but also in the horizontal direction. However, as only the bottom region of the trench is etched, the capacitor surface area, although enlarged, is not maximized.
In the International Electron Devices Meeting Technical Digest, 1995, an article teaching of a process for creating a bottle shaped capacitor, by T. Ozaki et al., entitled, "0.228 mm.sup.2 TRENCH CELL TECHNOLOGIES WITH BOTTLE-SHAPED CAPACITOR FOR 1GBIT DRAMs", formulates a capacitor with a larger diameter than the opening for the storage node. A collar oxide is formed at the upper portion of the trench by selective oxidation. In-situ phosphorous doped polysilicon is deposited and phosphorous doping is then performed into the trench side wall at the capacitor portion to form a buried plate electrode. The poly-silicon is removed by chemical dry etching and the diameter of the trench under the collar oxide is enlarged at the same time. The in-situ phosphorous doping used in Ozaki creates a buried plate region (plate electrode). There is no doping process step specifically tailored to control the etch rate.
In U.S. Pat. No. 5,629,226 issued to Ohtsuki on May 13, 1997, entitled, "METHOD OF MANUFACTURING A BURIED PLATE TYPE DRAM HAVING A WIDENED TRENCH STRUCTURE", a combination of protecting the upper side walls of a trench and etching doped silicon at the bottom of the trench forms a bottle shaped capacitor. The upper portion of the trench, including the opening portion is a cylinder of diameter R, while the lower portion thereof including the bottom portion is a sphere of diameter R.sub.max, with R.sub.max greater than R. The lower portion of the trench is widened by an isotropic chemical dry etching (CDE) process; pre-doping of the lower trench portion is not employed to control the etch rate. A plurality of buried plate diffusion regions surrounding the lower portions of the trenches are then integrally connected by a heat treatment process.
In these buried plate type trench capacitor DRAM designs, trench to trench dimension remains close to or at a minimum critical dimension that a given lithographic technique can define to maximize density. Thus, the dimensional control of bottle etching becomes critical. The existing prior art for creating bottle shaped trenches by dry etching lacks precise control as a result of not having an associated etch stop.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a controlled bottle trench capacitor for DRAM Storage Nodes.
A further object of the present invention is to provide a buried plate type DRAM in which the buried plate surrounds the entire bottle capacitor below the neck.
Still other objects of the invention will in part be obvious and will in part be apparent from the specification.